In the continuing trend to higher memory capacity, the size of a unit cell has been continuously decreased in order to increase the packing density of memory devices. The reduced unit cell size results in a decreased capacitor area of a DRAM unit cell, which comprises a capacitor for use as an information storage unit and a switching transistor connected to the capacitor. The decreased capacitor area means decreased cell capacitance, and it results in lowered read-out capability of the memory cell and increased soft error.
As one approach to solve the above-mentioned problem, capacitors having three-dimensional structures have been proposed in an attempt to increase an effective capacitor area in a unit cell. These types of capacitors usually have a lower electrode in the shape of a fin, a box, or a cylinder. However, the manufacturing processes for forming the three-dimensional capacitors may be so complicated as to generate defects.
Another approach is increasing the capacitance per unit capacitance area. Examples of this approach are a MIM (Metal-Insulator-Metal) capacitor and a MIS (Metal-Insulator-silicon) capacitor. The structure of the MIS capacitor includes a lower electrode formed of a metal, upper electrode formed of silicon and a capacitor dielectric layer interposed between the lower electrode and the upper electrode. The MIS capacitor has usually been used in DRAM devices having a memory capacity under 16-mega bits. The structure of the MIM capacitor includes a lower electrode formed of a metal, an upper electrode formed of the same metal or another metal, and a capacitor dielectric layer interposed between the lower electrode and the upper electrode. The MIM capacitor generally has better capacitance and leakage current characteristics compared to the MIS capacitor. Therefore, the MIM capacitor has been used as a capacitor in many DRAM devices having a memory capacity of 16-mega bits or more.
In the MIM capacitor, the lower electrode is usually made of a noble metal or its oxide. The noble metal includes platinum, ruthenium, iridium, rhodium and osmium. Each of the materials of the lower electrode is required to have a low work function value and not be reactive to the capacitor dielectric layer. Ruthenium is most widely used in the industry as a material of the lower electrode. This is because ruthenium can easily etched, especially in a plasma environment having oxygen, and its oxide, i.e., ruthenium oxide, is a good electrically conductive material.
Generally, a PVD (Physical Vapor Deposition) method and a CVD (Chemical Vapor Deposition) method can be used to form lower and upper electrodes of the MIM capacitors, but the CVD method is more widely used because a layer formed thereby is more conformable to a step difference of an underlaid structure. The conventional CVD method for forming a noble metal layer includes producing a metal organic source and oxygen into a processing chamber. The oxygen continuously decomposes the metal organic source to form the noble metal layer on a heated substrate.
FIG. 1 is a graph showing leakage current characteristics of MIM capacitors formed by the conventional CVD and PVD methods. The horizontal axis represents applied voltage into two electrodes of the MIM capacitors and the vertical axis represents corresponding leakage current. Ruthenium is used as material for lower and upper electrodes of the MIM capacitors, and tantalum oxide is used as a material for the capacitor dielectric layers. In the conventional method for forming the MIM capacitor, a capacitor dielectric layer is first formed on the lower electrode. The capacitor dielectric layer is then subjected to a crystallization annealing which is performed at 700° C. for 30 minutes in a nitrogen atmosphere in order to increase the capacitance of the capacitor. The upper electrode is formed on the capacitor dielectric layer. Subsequently, the upper electrode is subjected to a curing, which is performed at 400° C. for 30 minutes in an oxygen atmosphere. The reference marks ‘▪’ represent data of a capacitor having a lower electrode made by the CVD method, and the reference marks ‘●’ represent data of a capacitor having a lower electrode made by the PVD method. As shown in the graph, the capacitor made by the CVD method has a large leakage current than the capacitor made by the PVD method.
According to the analysis of present inventors, the large leakage current problem in the capacitor having the lower electrode made by the CVD method is due to impurities, e.g., carbons. The impurities are produced in the lower electrode when the metal organic source gas is not completely decomposed during the CVD process for forming the lower electrode. The impurities are thought to suppress the crystallization of the capacitor dielectric layer. Moreover, the impurities may induce defects in the capacitor dielectric layer, even though the impurities are too small amount to be detected by SIMS (Secondary Ion Mass Spectrometry) analysis. The defects act as sources of the leakage current.
On the other hand, the impurities react with the capacitor dielectric layer and form an unfavorable layer having a low dielectric constant between the capacitor dielectric layer and the lower electrode during the crystallization annealing. Therefore, a Tox (effective silicon oxide thickness) value may also be increased. The Tox value represents an effective thickness of a capacitor dielectric layer of a capacitor on the assumption that the capacitor dielectric layer was made of silicon oxide. Therefore, the increased Tox value means that capacitance per unit capacitor area is decreased.
Accordingly, the need remains for method for forming capacitors so that a high capacitance per unit area is maintained.